1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices, and in particular the present invention relates to a nonvolatile semiconductor memory device having uniform operational characteristics for memory cells.
This application claims priority to Korean Patent Application No. 2005-83921, filed on Sep. 9, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A nonvolatile semiconductor memory device comprises a plurality of memory cells, each of which comprises a floating gate and a control gate. A NAND-type nonvolatile semiconductor memory device comprises a plurality of cell strings, each of which comprises a group of memory cells that are connected in series. In a memory cell, a data bit is programmed or erased by creating a predetermined voltage difference between the control gate and a channel region of the memory cell. In accordance with the voltage difference created within the cell, electrons may be injected into the floating gate from the channel region through a tunneling current, or may move from the floating gate into the channel region. Here, the potential at the floating gate is determined by the ratio of the capacitance between the control and floating gates and the capacitance between the floating gate and the channel region.
FIG. 1 is a circuit diagram showing a cell string of a conventional NAND-type nonvolatile semiconductor memory device. Referring to FIG. 1, one end of the conventional cell string is connected to a bit line BL through a selection transistor SG1, while the other end of the cell string is connected to a source line SL through the other selection transistor SG2. As nonvolatile semiconductor memory devices have become more densely integrated, the intervals between adjacent memory cells, such as memory cells MC1˜MC32, have decreased in size. Due to the decrease in interval size, the floating gate of the memory cell is an important factor in view of the capacitance coupled between floating and control gates of adjacent memory cells, as well as in view of capacitance coupled with the channel region of the memory cell.
In the cell string of the conventional nonvolatile memory device of FIG. 1, memory cells MC1 and MC32 are adjacent to the selection transistors SG1 and SG2, respectively. A memory cell MC2 is located on one side of memory cell MC1, and selection transistor SG1 is located on the other side of memory cell MC1. Also, a memory cell MC31 is located on one side of the memory cell MC32, and selection transistor SG2 is located on the other side of memory cell MC32. In addition, selection transistors SG1 and SG2 each have a different structure and operational voltage than that of memory cells MC1˜MC32. Therefore, memory cells MC1 and MC32 adjacent to selection transistors SG1 and SG2, have different capacitive conditions than memory cells MC2˜MC31.
Thus, in the conventional NAND-type nonvolatile semiconductor memory device, outer memory cells MC1 and MC32, which are adjacent to selection transistors SG1 and SG2, respectively, operate with different operational characteristics than memory cells MC2˜MC31.